The application is based upon and claims the benefit of priority from the prior Japanese Patent Application Nos. 2002-233561, filed on Aug. 9, 2002 and 2002-181742, filed on Jun. 21, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an A/D converter (analog/digital converter) for converting an inputted analog signal into a digital signal, and is particularly suitable for being used for a successive approximation type A/D converter for converting an analog signal into a digital signal by a successive comparison operation.
2. Description of the Related Art
A successive approximation type A/D converter is presently known as an A/D converter, which can be realized with a simple circuit constitution and produced at comparatively low cost with high matching property with a CMOS process, requires less time for A/D conversion that is the conversion processing from an analog signal to a digital signal, and has a wide range of product uses. In the successive approximation type A/D converters, the one using a double stage DAC (a D/A converter: a digital/analog converter) for converting a comparison digital signal into a comparison analog signal can realize an A/D converter (: an analog/digital converter) with high resolution in a small mounting area.
A successive approximation type A/D converter using the double stage DAC is constituted of a double stage DAC constituted of a main DAC for deciding a most significant bit (MSB) side and a sub DAC for deciding a least significant bit (LSB) side, a comparator circuit, and a control circuit (control method) called an xe2x80x9cSAR (successive approximation register)xe2x80x9d. At first, an analog potential set by the main DAC and an input analog potential are compared, whereby high-order bits are decided. The analog potential set by the main DAC corresponding to the decided high-order bits and the analog potential set by the sub DAC are added, and a sum of them and the inputted analog potential are compared, whereby low-order bits are decided.
The double stage DACs are broadly divided into four constitutions (the main DAC+the sub DAC) as shown below depending on whether the main DAC and the sub DAC are realized by capacitor arrays, or resistor strings.
(1) Capacitor array+capacitor array type (hereinafter, called C-C type)
(2) Resistor string+capacitor array type (hereinafter, called R-C type)
(3) Capacitor array+resistor string type (hereinafter, called C-R type)
(4) Resistor string+resistor string type (hereinafter, called R-R type)
Constitution examples of a successive approximation type A/D converter using a C-R type double stage DAC are disclosed in, for example, Japanese Patent Laid-open No. 59-163913 and Japanese Patent Laid-open No. 57-55614.
A conventional successive approximation type A/D converter using a C-R type double stage DAC will be explained hereinafter.
FIG. 1 is a diagram showing a circuit constitution of the conventional successive approximation type A/D converter.
The successive approximation type A/D converter in FIG. 1 includes an input terminal 3 to which an input potential Vin is applied, nodes 24 to 27, nodes 40 to 44, a switch circuit 21, a switch circuit 22, a switch circuit 23, a switch circuit 121, a comparator 30, a successive approximation control circuit 32xe2x80x2, resistors R0 to R15, and capacitors C1 to C5. The successive approximation control circuit 32xe2x80x2 controls an operation of each of the switch circuits 21, 22, 23, 121, and the like.
The resistors R0 to R15 and the switch circuit 121 constitute a 4-bit sub DAC, and the capacitors C1 to C5 and the switch circuit 21 (and 22 and 23) constitute a 4-bit main DAC. As for the capacitors C1 to C5 constituting the main DAC, if a capacitance value of each of C1 and C2 is assumed to be Cx, C3 is weighted to be 2Cx, C4 is weighted to be 4Cx and C5 is weighted to be 8Cx. To secure relative accuracy, the sampling capacitors C3 to C5 are generally realized by connecting, for example, two, four or eight of certain unit capacitors Cx in parallel.
When sampling is performed, all of the capacitors C1 to C5 are connected to an analog input terminal 3 (Vin) via the switch circuit 21, the node 25 and the switch circuit 22, and charged to the input potential Vin. In this situation, the switch 23 is controlled so that the node 24 is at GND.
After sampling is finished, a comparison operation is started, and digital data corresponding to the input potential Vin is decided in sequence from the MSB. More specifically, the switch 23 is opened to bring the node 24 into a floating state, for example, the nodes 40 to 43 are connected to the GND via the switches 21 and 22, and the node 44 is connected to a reference potential Vref (a terminal 1). By the connection, electric charge stored by the input potential Vin at the sampling time is redistributed to the sampling capacitors Cl to C5, and a potential of the node 24 becomes (Vref/2xe2x88x92Vin) The node 24 is connected to an input of the comparator 30, and it can be determined according to a potential of the node 26 being an output of the comparator 30 whether the analog input potential Vin is larger or smaller than xc2xd of the reference potential Vref.
In the above-described connection, the node 44 is connected to the reference potential Vref, and the other nodes 40 to 43 are connected to the GND. Namely, 8Cx of C5 are connected to the reference potential Vref, and the sum total of 8Cx of the remaining C1 to C4 are connected to the GND. Generally, when the number of unit capacitors Cx connected to the reference potential Vref is assumed to be m, and the number of the remaining unit capacitors Cx connected to the GND is assumed to be (16xe2x88x92m), the potential Vx of the node 24 is
Vx=(m/16)Vrefxe2x88x92Vin.
For example, when the node 41 is connected to Vref, and the remaining nodes 40, 42, 43 and 44 are connected to the GND, m equals 1, and therefore the potential of the node 24 is (Vref/16xe2x88x92Vin).
Accordingly, by successively changing m, it is possible to change the potential of the node 24 successively in increments of Vref/16, and the MSB side of the digital data (high-order 4 bits) can be decided.
Next, with m that is decided as described above being assumed to be mxe2x80x2, mxe2x80x2 of the unit capacitors Cx out of C2 to C5 are connected to the reference potential Vref, the remaining (15xe2x88x92mxe2x80x2) of the unit capacitors Cx out of C2 to Cs are connected to the GND, and the node 40 of one of the unit capacitor Cx of C1 is connected to the sub DAC (R0 to R15, and the switch circuit 121). The potential of the node 40 is changed in increments of Vref/16 by the sub DAC, whereby the potential of the comparator input 24 can be changed in increments of Vref/256. Consequently, the LSB side of the digital data (low-order 4 bits) is decided, and 8-bit digital data in total can be obtained.
FIG. 2 is a diagram showing another circuit constitution of the conventional successive approximation type A/D converter.
In FIG. 2, capacitors C1 to CS and a switch group 21 (switches SWC1 to SWC5) constitute a capacitor type DAC (main DAC) with 4-bit accuracy, and resistors R0 to R15 and a selector 121 constitute a resistor type DAC (sub DAC) with 4-bit accuracy. As for the capacitors C1 to CS, if the capacitance value of each of the capacitors Cl and C2 is Cx, a capacitance value of the capacitor C3 is weighted to 2Cx, a capacitance value of the capacitor C4 is weighted to 4Cx (=22Cx) , and a capacitance value of the capacitor CS is weighted to 8Cx (=23Cx) The capacitors C3, C4 and CS are generally constituted by connecting, for example, two, four, and eight of the unit capacitors Cx in parallel, respectively, to secure relative accuracy. Resistance values of the resistors R0 to R15 are equal to each other.
When the successive approximation type A/D converter shown in FIG. 2 converts an analog input signal inputted from an input terminal 3 into digital data, it firstly performs sampling of the potential Vin of the inputted analog input signal, and charges the capacitors C1 to C5 according to the potential Vin. In this situation, a successive approximation control circuit 32 controls the switch group 21 and a switch 22 according to control signals S2 and S3, whereby one ends of the capacitors Cl to C5 are connected to the input terminal 3 via lines L1 to L5, the switch group 21 and the line L7.
The successive approximation control circuit 32 controls a switch NM1 according to a control signal SPL1. The control of the switch NM1 is performed such that the switch NM1 is in an ON state, and a potential Vx of an input node 4 is equal to a logical threshold voltage VTL of a comparator 31.
As described above, the potential Vx of the node 4 is made the logical threshold voltage VTL, and the potential Vin of the analog input signal is supplied to the one ends of the capacitors C1 to C5, whereby sampling of the potential Vin of the analog input signal is performed, and electric charge corresponding to the potential Vin is stored in the capacitors C1 to C5.
After sampling of the potential Vin of the analog input signal is finished, the successive approximation type A/D converter performs a comparison operation of sequentially deciding digital data for each bit from the most significant bit (MSB) to a low-order side.
The successive approximation control circuit 32 firstly sets the switch NM1 into an OFF state so that the potential Vx of the input node 4 is decided by redistributing the electrical charge, which are stored in the capacitors C1 to C5 by sampling, into the capacitors C1 to C5. The successive approximation control circuit 32 controls the switch group 21 and the switch 22 to connect the one ends of the capacitors C1 to C4 to the ground via the switch 22, and connect the one end of the capacitor C5 to a power supply terminal 1 for supplying the reference potential Vref. As a result, the electric charge stored in the capacitors C1 to C5 by sampling is redistributed, and the potential Vx of the input node 4 becomes (VTL+Vref/2xe2x88x92Vin).
The comparator 31 determines whether the potential Vx of the input node 4 is lower than the logical threshold voltage VTL or not, namely, whether the potential Vin is higher than the potential Vref/2 or not. As a result of the determination, when the potential Vin is higher than the potential Vref/2, the determination output S1 from the comparator 31 is at a high level (xe2x80x9cHxe2x80x9d), and when the potential Vin is lower than the potential Vref/2, the determination output S1 is at a low level (xe2x80x9cLxe2x80x9d). The successive approximation control circuit 32 decides a value of the MSB to be xe2x80x981xe2x80x99 when the determination output S1 is xe2x80x9cHxe2x80x9d, and decides the value of the MSB to be xe2x80x980xe2x80x99 when the determination output S1 is xe2x80x9cLxe2x80x9d.
When the decided value of the MSB is xe2x80x981xe2x80x99, the successive approximation control circuit 32 controls the switch group 21 and the switch 22 to connect the one ends of the capacitors C4 and C5 to the power supply terminal 1 and connect the one ends of the capacitors C1 to C3 to the ground. As a result, the potential Vx of the input node 4 becomes (VTL+3 Vref/4xe2x88x92Vin).
On the other hand, when the decided value of the MSB is xe2x80x980xe2x80x99, the successive approximation control circuit 32 controls the switch group 21 and the switch 22 to connect the one end of the capacitor C4 to the power supply terminal 1 and connect the one ends of the capacitors C1 to C3 and C5 to the ground.
As a result, the potential Vx of the input node 4 becomes (VTL+Vref/4xe2x88x92Vin).
Similarly to what is described above, the comparator 31 determines whether the potential Vx of the input node 4 is lower than the logical threshold voltage VTL or not, whereby the successive approximation control circuit 32 decides the value of the lower bit than the MSB by 1 bit.
Similarly, the successive approximation control circuit 32 controls the switch group 21 and the switch 22 to connect the one end of the capacitors C1 to C5 to the power supply terminal 1 or the ground according to the decided value of the bit. Then, the comparator 31 determines by comparison whether the potential Vx of the input node 4 is lower than the logical threshold voltage VTL of the comparator 31 or not, whereby the successive approximation control circuit 32 decides the digital data in sequence from the high order side.
Here, if, for example, the switch group 21 and the switch 22 are controlled, and the one ends of the capacitors C1 and C3 to C5 are connected to the ground, and the one end of the capacitor C2 is connected to the power supply terminal 1, the potential Vx of the input node 4 becomes (VTL+Vref/16xe2x88x92Vin). Namely, the capacitor type DAC (main DAC) of the successive approximation type A/D converter shown in FIG. 2 controls the switch group 21 by setting the capacitance value Cx, which is {fraction (1/16)} of the total capacitance values 16Cx of the capacitors C1 to C5, as a unit, whereby it selectively connects one ends of the capacitors C1 to C5 to the power supply terminal 1 or the ground. As a result, the successive approximation type A/D converter shown in FIG. 2 can change the potential Vx of the input node 4 in increments of Vref/16 by the capacitor type DAC, and can decide high-order 4-bit digital data.
After the high-order 4-bit digital data is decided, the successive approximation control circuit 32 controls the switch group 21 and the switch 22 according to the decided value of high-order 4 bits to connect the one ends of the capacitors C2 to C5 to the power supply terminal 1, or the ground via the switch 22. Further, the successive approximation control circuit 32 controls a selector 121 according to corresponding relationship shown in FIG. 3 that will be described later to supply a potential corresponding to a digital code to the one end of the capacitor C1 via an output line L71 of the resistor type DAC, a switch SWC1 and the line L1.
FIG. 3 is a diagram showing corresponding relationship of an input digital code and a potential outputted via the output line L71 in the resistor type DAC shown in FIG. 2. As shown in FIG. 2, the resistors R0 to R15 with equal resistance values are connected in series between the power supply terminal 1 and the ground terminal 2, whereby the resistor type DAC can generate 16 potentials (Vref/16xc3x97n: n is an integer from 0 to 15) by changing the potential in increments of Vref/16 as shown in FIG. 3.
When the value of low-order 4 bits is decided, the successive approximation control circuit 32 only closes the switch in the selector 121, which is connected to an interconnection point of the resistor R7 and the resistor R8 at first, and controls the other switches in the selector 121 to open (input digital code xe2x80x9c1000xe2x80x9d). Then, in the state in which the potential of Vref/2 (8 Vref/16) is supplied to the one end of the capacitor C1, the potential Vx of the input node 4 and the logical threshold voltage VTL of the comparator 31 are compared and determined by the comparator 31.
As a result of comparison and determination, when the potential Vx of the input node 4 is lower than the logical threshold voltage VTL, the switch in the selector 121, which is connected to the interconnection point of the resistor R11 and the resistor R12, is closed, and the other switches in the selector 121 are controlled to open (input digital code xe2x80x9c1100xe2x80x9d). Meanwhile, when the potential Vx of the input node 4 is higher than the logical threshold voltage VTL, only the switch in the selector 121, which is connected to the interconnection point of the resistor R3 and the resistor R4, is closed, and the other switches in the selector 121 are controlled to open (input digital code xe2x80x9c0100xe2x80x9d).
Then, the potential Vx of the input node 4 and the logical threshold voltage VTL are compared and determined in the comparator 31. The same operations are repeatedly performed, and the value of low-order 4 bits is decided by each bit in sequence from the higher order side.
As described above, the resistor type DAC shown in FIG. 2 changes the potential, which is supplied to the one end of the capacitor C1 having the capacitance value Cx which is {fraction (1/16)} with respect to the total capacitance value 16Cx of the capacitors C1 to C5, in increments of Vref/16. As a result, the successive approximation type A/D converter shown in FIG. 2 can change the potential Vx of the input node 4 in increments of Vref/256, and digital data of 8 bits in total can be decided.
The conventional successive approximation type A/D converter as shown in FIG. 1 and FIG. 2 includes sixteen unit capacitors Cx and sixteen unit resistors, whereby the A/D converter with 8-bit accuracy is realized. In the case of constituting an A/D converter with 8-bit accuracy using a single stage DAC with only the capacitor type DAC or the resistor type DAC, it is necessary to include 256 unit capacitors or 256 unit resistors. Accordingly, in the case of constituting the A/D converter with the same accuracy, the number of components can be sharply reduced by using a double stage DAC. In the successive approximation type A/D converter shown in FIG. 1 and FIG. 2, the accuracy of the resistors in the resistor type DAC is only 4-bit accuracy, and it can be constituted by the resistor type DAC with a small area, which is also one of the advantages.
Namely, the conventional successive approximation type A/D converter reduces the area of the capacitors by using the double stage DAC, and further reduces the area of the resistor type DAC using the resistor string for the sub DAC.
The high resolution successive approximation type A/D converter with the small area at a high speed, which is produced in the CMOS process capable of production at comparatively low cost, is in practical use.
In recent years, a demand for speed enhancement of the A/D converter is increasing more and more, and speed enhancement of the successive approximation type A/D converter capable of constituting the circuit with a small area is strongly desired. In the conventional circuit shown in FIG. 1, there arises the problem of a delay in switching, when the potential of the node 27, which is the output of the sub DAC (R0 to R15 and the switch circuit 121), is set at, for example, Vref/2. This is because a switch circuit is generally realized by a CMOS transfer gate, and therefore when the power supply voltage (Vref) is low, the ON resistance becomes high at both the PMOS and NMOS with respect to the source/drain voltage at Vref/2, which increases a delay time in the switch circuit 121.
Following the development of finer integrated circuits and the like in recent years, power supply voltage in the integrated circuits and the like is reduced, and reduction in the power supply voltage is also demanded in the A/D converters. Reduction in the power supply voltage is also strongly demanded in the successive approximation type A/D converter capable of constituting a circuit with a small area.
For example, reduction in the power supply voltage in the conventional successive approximation type A/D converter using the C-R type double stage DAC as shown in FIG. 2 is considered.
When the conventional successive approximation type A/D converter as shown in FIG. 2 is produced in the CMOS process, the transfer gate as shown in FIG. 4 is generally used for each switch in the selector 121 and the switch group 21. The above-described transfer gate is constituted of a P-channel transistor (PMOS transistor) PMTr and an N-channel transistor (NMOS transistor) NMTr.
FIG. 5 is a graph showing relationship of an input potential Vin and ON resistance Ron, the input potential Vin being inputted from an input terminal T1 when 0V and a reference potential (power supply voltage for comparison) Vref (+3V or +5V or the like) are applied to the gate electrodes of the PMOS transistor PMTr and the NMOS transistor NMTr, respectively, as shown in FIG. 4 (when the transfer gate is in an ON state). As shown in FIG. 5, when the input potential Vin is sufficiently low (for example, 0V), the NMOS transistor NMTr is sufficiently in the ON state (ON resistance becomes small)(area (B)), while when the input potential Vin is sufficiently high (for example, VrefV), the PMOS transistor PMTr is sufficiently in the ON state (ON resistance becomes small) (area (A)). Accordingly, the input potential Vin is transmitted to an output end T2 as an output potential.
However, as the input potential Vin becomes higher from the sufficiently low value, the ON resistance becomes larger. Similarly, as the input potential Vin becomes lower from the sufficiently high value, the ON resistance becomes larger. For example, when the potential is xc2xd times as low as the reference potential Vref, both the PMOS transistor PMTr and the NMOS transistor NMTr are in the state with the large ON resistance, and the ON resistance of the transfer gate becomes the maximum.
As described above, the switch group 21 for controlling the capacitor type DAC supplies the ground GND or the reference potential Vref to the one ends of the capacitors C2 to C5 during a comparison operation. Meanwhile, the switch inside the selector 121 for controlling the output potential from the resistor type DAC outputs the potential about xc2xd times as low as the reference potential Vref in some case as, for example, when the digital code is xe2x80x9c1000xe2x80x9d in the corresponding relationship as shown in FIG. 3.
When the potential substantially xc2xd times as low as the reference potential Vref is transmitted in the switch inside the selector 121, the gate-source voltage of the MOS transistors PMTr and NMtr constituting the transfer gate becomes about Vref/2. Accordingly, when the potential substantially xc2xd times as low as the reference potential Vref is outputted, the ON resistance of the transfer gate becomes large as shown in FIG. 5, which becomes interference in reduction of the power supply voltage.
Namely, in the conventional successive approximation type A/D converter using the C-R type double stage DAC, the gate-source voltage of the MOS transistors PMTr and NMTr becomes about Vref/2 when the potential of substantially xc2xd times as low as the reference potential Vref is outputted from the resistor type DAC. Consequently, in reduction of the power supply voltage in the conventional successive approximation type A/D converter, such a problem exists that a normal operation cannot be performed only at a power supply voltage up to a voltage at which the voltage of Vref/2 is about the threshold voltage VTH of the MOS transistors PMTr and NMTr, namely, the power supply voltage of about 2VTH.
In the conventional successive approximation type A/D converter using the C-R type double stage DAC, as for a current passing through the resistor type DAC, the current of the same value passes all through the sampling period and comparison operation period. However, a time constant required of the resistor type DAC during the sampling period is generally larger than a time constant required in the comparison operation. Accordingly, during the sampling period, the resistor type DAC wastes electric power.
A first object of the present invention is to provide a circuit with a processing time of A/D conversion of a successive approximation type A/D converter being reduced.
A second object of the present invention is to provide a circuit which makes it possible to operate the successive approximation type A/D converter at low power supply voltage, without increasing a delay time in resistor DACs even when the power supply voltage is low.
A third object of the present invention is to make it possible to reduce power consumption required for all the processes of A/D conversion in the successive approximation type A/D converter.
The A/D converter according to the present invention includes a capacitor type D/A conversion circuit including a capacitor array constituted of a plurality of capacitors for sampling an input potential and storing electric charge, a first resistor type D/A conversion circuit for generating a desired potential by potential division, a second resistor type D/A conversion circuit for generating a desired potential by potential division, a first signal path for adding an output of the first resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, a second signal path for adding an output of the second resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, and a comparing circuit for determining whether a potential of the output of the capacitor type D/A conversion circuit is higher or lower than the input potential.
In the above-described constitution, for example, in the case of 8-bit A/D conversion, it is sufficient if the switch circuits of the first resistor type D/A conversion circuit and the second resistor type D/A conversion circuit are each a selector of 4:1 for deciding 2 bits, as compared with the switch circuit of the sub DAC of the conventional circuit being a selector of 16:1 for deciding low-order 4 bits, and the scale of the switch circuits can be sharply reduced. In the switch circuit, junction capacitance of a MOS transfer gate constituting the switch works as parasitic capacitance, which brings about a delay in a signal change, and therefore the time required for the comparison process of A/D conversion is increased. In the constitution of the present invention, the switch circuits of the first resistor type D/A conversion circuit and the second resistor type D/A conversion circuit can be made small-scaled, therefore sharply reducing the parasitic capacitance and making it possible to reduce the time required for the comparison process.
When the number of bits of the capacitor DAC is reduced and the number of bits of the resistor DAC is increased in order to reduce the sampling time, an increase in a delay time in the resistor DAC can be reduced. Accordingly, it is possible to reduce the sampling time substantially without increasing the comparison time out of the conversion time of the A/D converter, and therefore the conversion time can be reduced.
According to another aspect of the present invention, in the above-described A/D converter, the first resistor type D/A conversion circuit is connected to the output of the capacitor type D/A conversion circuit via capacitor being a predetermined times as much as minimum unit capacitance of a plurality of capacitors, and a range of the output of the first resistor type D/A conversion circuit exists only in either of an upper half or lower half among a range from a first potential to a second potential, which is divided by a resistor string.
In this constitution, in the case of a resistor string dividing Vref into 16, for example, the output of the first resistor type D/A conversion circuit is set in a voltage range as high as possible such as from 12 Vref/16 to 15 Vref/16, whereby the switch circuit of the resistor type D/A conversion circuit can be used in the area with ON resistance being low. At the transfer gates of PMOS and NMOS, the ON resistance becomes high at the voltage around xc2xd of the power supply voltage (Vref), and a high-speed operation becomes difficult, but use of the voltage near the power supply voltage (Vref) makes it possible to reduce a delay time, whereby enhancement in speed of the conversion processing can be attained.
Another mode of the A/D converter of the present invention includes a capacitor type D/A conversion circuit for outputting a potential corresponding to high-order L bits of inputted comparison digital data, a plurality of resistor type D/A conversion circuits for outputting in accordance with a value of low-order M bits potentials obtained by dividing supplied power supply voltage in a predetermined combination, a plurality of coupling capacitors connected between output terminals of the resistor type D/A conversion circuits and an output end of the capacitor type D/A conversion circuit, a control circuit and a comparing circuit, and a plurality of resistor type D/A conversion circuits are respectively controlled so that a sum of output potentials of a plurality of resistor type D/A conversion circuits, weighted based on the coupling capacitors, becomes equal to a potential corresponding to the value of the low-order M bits of the comparison digital data. As a result, it becomes possible to add and output the output potentials of a plurality of resistor type D/A conversion circuits, without outputting the potential itself which causes a problem in the reduction in the power supply voltage.
Further, when an initial potential supply circuit for outputting a predetermined potential to one of the plurality of coupling capacitors during sampling of the input analog signal is further included, it becomes possible to reduce power consumption during sampling and reduce power consumption required for the A/D conversion process by providing the initial potential supply circuit with less power consumption than the resistor type D/A conversion circuit used for the comparison operation separately from the resistor D/A conversion circuit.